The present invention relates to a semiconductor memory device, and particularly to a DRAM for performing high-speed read and write operations.
Electronic apparatus using semiconductor devices, such as workstations and personal computers, have made great strides in increasing their operational speed in recent years. Such electronic apparatus typically includes DRAM type memory devices and attain increased operational speed based on the EDO (Extended Data Out) DRAMs, page mode, etc. However, at present, DRAMs cannot operate as fast as an MPU which is another major component part of such electronic apparatus. Accordingly, the MPU operates slower, thereby decreasing performance of the system as a whole. Therefore, it would be desirable to increase the speed of DRAMs.
An example of the sequence of operation of the conventional DRAM will be explained with reference to FIG. 1. When the control signal /RAS goes low, a row address signal R1 is provided from an external device, and a word line WL1 which is selected by the row address signal R1 is activated. Each word line is raised to a step-up voltage of 5 V which is higher than the power voltage of 3 V, for example, in order to read cell information from the selected memory cell efficiently and quickly or write cell information to the selected memory cell firmly and quickly. Cell information is read from the memory cell connected to the selected word line WL1 onto one of bit line pairs BL and /BL, creating a small voltage difference emerging between the bit line pair BL and /BL.
Subsequently, a sense amplifier activation signal LE is provided to the sense amplifier that is connected to the bit line pairs BL and /BL so that the small voltage difference between the bit line pair BL and /BL is amplified, and the retrieved cell information is written back to the memory cell.
When another external control signal /CAS goes low, a bit line pair BL and /BL are selected by an external column address signal, causing the sense amplifier of the selected bit line pair BL and /BL to place its output signal as cell information on the data bus.
Subsequently, when the control signals /RAS and /CAS go high, the word line selecting operation ends, causing the word line WLl to fall to the low level. In addition, the sense amplifier is inactivated and the bit line pair selecting operation ends, causing the bit line pair BL and /BL, from which cell information has been read, to be reset to an intermediate voltage. Thus, a one cycle read operation is completed.
Subsequently, when the control signal /RAS goes low again, another row address signal R2 is provided, causing another word line WL2 to rise to the high level, and the read operation proceeds as explained above.
The read cycle includes a certain wait time t1 after the control signal /RAS has gone high at the end of the previous read operation until the control signal /RAS goes low at the beginning of the next read operation. This wait time t1 is provided to allow the high-level word line WL1 in the previous cycle to fall enough before the word line WL2 selected in the next cycle is activated, thereby preventing a double selection of the word lines WL1 and WL2. The wait time t1 needs to be as long as a 1/3 cycle time of read operation, and therefore reduction of the wait time t1 contributes significantly to the speed-up of reading. However, it is difficult to reduce the wait time t1 without altering the basic design.
Attempting to increase the output power of the word line drive circuit so as to pull down word lines quickly to the low level invites read errors caused by increased power noise, or even much slower pull-down of word lines due to a lack of output current of the voltage step-up power circuit.
Another attempt of lowering the high-level voltage of word lines to speed up the pull-down of the word lines results in a reduced charge to the memory cells, which necessitates a shorter refresh period for cell information and increased power consumption.
An object of the present invention is to provide a semiconductor memory device capable of speeding up the read-out of cell information and having low power consumption.